Manual placement of BUFGMUX instances in a Spartan3AN chip

Something to be aware of while playing with manual placement of BUFGMUX in a Spartan 3AN chip. Here is an example of using a BUFGMUX to choose between two clocks coming into the device. Selecting two global clock inputs (say GCLK4 and 5) according to the graph in Xilinx UG331 "Clocking Infrastructure" paragraph (pg47)[1] as partly shown in figure a and coding them as follow:

clock_selector: BUFGMUX port map ( S => SEL_in, I0 => GCLK5, I1 => GCLK4, O => clk_s);

Leaving the Place And Route tool to do its job it routed the signal using BUFGMUX_X2Y11 as in figure b.

Now instructing the PAR tool to explicitly use BUFGMUX_X2Y10 with the user constraint in the ucf file:

INST "clock_selector" LOC = BUFGMUX_X2Y10

as shown in figure c

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results in two errors:

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <clock_selector> is placed at site <BUFGMUX_X2Y10>. The IO component <GCLK5> is placed at site <D9>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "GCLK5" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <clock_selector> is placed at site <BUFGMUX_X2Y10>. The IO component <GCLK4> is placed at site <C10>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "GCLK4" CLOCK_DEDICATED_ROUTE = FALSE; >

It is not very clear in Xilinx documentation what the restrictions for allocating clocks to inputs of a BUFGMUX are but conveniently in the Spartan3A it seems to work this way: In a BUFGMUX pair if the Ynumber is even then the even numbered clock should go to the even numbered input. So for example if using BUFGMUX_X2Y10 then GCLK4 should connect to I0 and GCLK5 to I1. See figure d below for mapping the global clocks to the X2 pair of BUFGMUX.

Figure d: Allowed clocks to BUFGMUX inputs combinations

Note however that BUFGMUX come in pairs so if using both inputs of X2Y10 then X2Y11 cannot be used. If trying to do so you will get an unroutable error from the PAR tool.

[1] UG331: Spartan-3 Generation FPGA User Guide - UG331 (v1.8) June 13, 2011